The issue of data confidentiality is a critical concern within the Ceph storage system, particularly given the limited security services provided by authentication and access control. To mitigate this risk, a proposed solution involves the implementation of a third-party security interface known as CephArmor. This cryptographic-based interface adds an extra layer of protection to data at rest, utilizing AES CBC, CTR, and GCM techniques to effectively safeguard against data leakage. By enhancing the security capabilities of Ceph's clustered storage solution, this solution offers a robust and effective approach to mitigating data confidentiality risks.
Objectives: Introducing CephArmor, Storage Security, High-performance Computing, Ceph, Cryptography

This project proposes improving FPGA device utilization and simplifying the synthesis flow by automating complex logic decisions with architecture awareness. Yosys, as a front-end for generating coarse-grained netlists, and Odin-II, as BLIF elaborator and partial mapper, are integrated into the VTR flow. Hard/soft logic trade-off decisions and heterogeneous logic inference have become available for Yosys coarse-grained BLIF files, while Yosys+Odin-II lowers resource consumption, shrinks final circuit footprint, and reduces overall routed wire length.

Implementing a heuristic partial mapping plugin in C, C++ for Verilog-to-routing/ODIN-II to optimize the configuration of soft blocks' designs. Indeed, we propose a method to modify circuit characteristics using a genetic algorithm during synthesis to adjust soft-logic circuit implementation in order to achieve the desired synthesis goal. [Read more]

We propose re-configurable hardware for compensating the computationally intensive parts of image processing application (filters) by Hardware/Software Co-design using DE0-Nano-SoC FPGA. Using the flexibility of software and the high performance of hardware, we utilized a virtual reconfigurable circuit (VRC) in combination with systolic cartesian genetic programming (CGP) to design the accelerator. The evolution algorithm for the requested filter is executed on the fabric and the VRC is reconfigured correspondingly on the FPGA till achieving the end goal. [Read more]

We propose a device to measure high and low blood pressure in addition to heart-beat rate. Utilizing a cuff, the blood pressure is measured with a pressure sensor by increasing the air pressure inside the cuff (usually up to 200 mmHg) and then decreasing the pressure slowly. In addition to hardware design, we used Atmega32 for Analog to Digital Converter (ADC) and Timer. [Read more]

We propose software that provides facial recognition using deep metric learning and neural networks. The software is written in Python, the network has been trained with the help of dlib library. Using Histogram of Oriented Gradients (HOG), we first transform a face image into a simple image with vectors showing the basic flow of lightness and darkness. Then using unique patterns of each face  we train our network to recognize and label faces [Read more]

Designed a digital oscilloscope, consisting of four parts of horizontal control, trigger control, vertical control, and the display, which was implemented on Altera DE0-Nano board.