The work done in the field of evolutionary algorithms to design and synthesize electronic circuits has yielded acceptable and reliable results, though there are still problems in achieving the main goal of this field and the evolution of complex circuits in an acceptable time. It has been a long time since the first ideas for the use of evolutionary algorithms for the automatic design and synthesis of electronic circuits were introduced. However, it can still be argued that this method has difficulty in obtaining practical solutions, especially for complex problems. One of the main reasons for the slow progress of evolutionary hardware is the lack of proper infrastructure to implement this method. Initially, the algorithm was implemented and evaluated separately using software simulation. Although this method has good flexibility, its execution time to converge to acceptable solutions, especially when the circuit is relatively complex, will be very long and practically unusable.

With the advent of reconfigurable hardware structures such as FPGAs, part or all of the algorithms can be executed on the hardware. In this way, the execution time of the algorithm and, in particular, the evaluation of the generated circuits, is done much faster. However, there are many limitations such as how to reconfigure and the amount of logic that can be used in FPGAs and other configurable hardware, which poses serious obstacles to the rapid growth of the field. FPGAs are the most serious infrastructure used by researchers in this field, and new advances in the technology of making these reconfigurable chips are very promising. Every year, manufacturers produce faster chips with more resources. Dynamic partial reconfiguration technology (DPR), recently introduced in the high-end chips of companies such as Xilinx and Altera, has attracted the attention of researchers and could pave the way for new innovations in the field of evolutionary hardware. Despite all these advances in the field of configurable chips, it should be noted that these technologies are still built for conventional circuit design and synthesis methods and are limited to use as an evolutionary hardware infrastructure.

We propose a hardware platform capable of synthesizing digital circuits. Due to the potential of evolutionary hardware in finding creative and optimal solutions, the use of this method has been considered. In fact, by implementing the hardware of an evolutionary algorithm, its execution time will be significantly reduced. Systolic Cartesian Genetic Programming is used as the basis of the evolutionary algorithm. The algorithm is designed on a DE0-Nano-SoC chip using Verilog hardware description language and synthesized and implemented by Quartus. Given that the circuit evaluation part is known as the main bottleneck of the evolutionary process, only this part is performed on the hardware along with calculating the suitability of chromosomes. The process of mutation and production of the next generation, along with the selection of superior chromosomes, is written entirely in software and in C++. Synthesis of digital circuits is done in a platform of a hardware and software co-design. The software part of the algorithm under the Linux operating system is run on a processor with ARM Cortex A9 architecture in the chip, and each chromosome is evaluated by a hardware accelerator implemented on the chip's reconfigurable logic.

Acknowledgment

I have defended my bachelor's thesis by completing and extending the prior work of Mr. Mirjahanian on this project. I would like to express my thanks to Mr. Mirjahanian and Dr. Salehi Eraslinasab for their valuable effort and aid in this project.

Date: September 10th, 2017