About

    I am Seyed Alireza Damghani, an FPGA/EDA developer with significant contributions to open-source tools like Verilog-to-routing (VTR), Yosys, ABC, and Odin-II. Specializing in hardware/software co-design and innovative hardware designs, I leverage advanced coding, design patterns, and debugging skills in Linux/Unix environments. My expertise includes device modelling for transceivers, peripherals, and high-voltage IOs, working on primitive generation and standard function data frameworks aligned with design intents and rule-based constraints, as well as proficiency in large-scale software architecture and modularization techniques.

    I engaged in diverse, practical projects during my bachelor's studies at the University of Tehran. I initiated a computational biology project to develop a Blood Pressure Measurement Device using ARM microprocessors like ATMEGA32, marking a significant advancement in my educational journey. Subsequently, I collaborated with the Embedded Systems Lab on compensating computationally intensive parts of image processing applications through hardware/software co-design using Xilinx Zynq-7000 and Altera DE2 FPGA boards. The university committee and Iran's largest Internet service provider, SHATEL, recognized this project as the best. I graduated with a B.Sc. in Computer Engineering from Iran's top electrical and computer engineering university.


    Having gained industrial experience, I pursued my master's degree in Computer Science in Canada. I led the development team to integrate the Yosys+Odin-II synthesis compiler into the Verilog-to-Routing open-source EDA tool, improving device utilization and automating logic decisions with architecture awareness. As the Odin-II maintainer in the VTR CAD flow, I enhanced the codebase, reviewed pull requests, fixed issues, and added new features.


    After joining Intel as an FPGA software engineer, I contributed to the development of the Quartus Compiler, focusing on analysis, elaboration, and synthesis processes, including constraint handling and HDL attribute processing. My experience includes formal verification with OneSpin, simulation using ModelSim/QuestaSim/VCS, implementing the Quartus hierarchy validation flow, working with signal tap and debug logic insertion techniques, and developing fuzz testing tools for design validation. I also developed regression models for post-synthesis timing estimation using machine learning techniques, enhancing accuracy and efficiency through feature extraction, feature engineering, and ensemble methods, and utilized ONNX for cross-code compatibility. 


    With more recent activity on device modelling, I have participated in the modelling and validation of peripheral IOs and transceiver subsystems, flexible and generic peripheral placement for converting design netlist graph to device netlist graph, and block configuration solution finders, as well as working on the integration of rule-based constraints onto the device netlist.


    On a personal side, I have gained experience fine-tuning open-source large language models like Llama 2 and Google BERT for industry-specific applications, applying retrieval-augmented generation to improve performance, and possessing a solid understanding of LLM architectures, attention mechanisms, and multi-layer perceptrons.​

You can access the complete version of my curriculum vitae, here.

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