Technology mapping is the transformation of a general Boolean logic network into a functional equivalent K-LUT network that can be implemented by the target FPGA device. Because an FPGA architecture is pre-determined, technology mapping is limited to the available resources. However, circuits can be optimized before the low-level synthesis phase. Odin-II, part of the Verilog-to-routing project, is responsible for synthesis and elaboration. In the partial mapping phase of Odin-II, some modifications are still possible for high-level modules-adder, multiplier-when there is no hard block available. When Odin-II performs partial mapping to create soft logic, we can choose which implementation of a high-level module works best with respect to the desired goals: area versus speed. In this paper, we describe a method to modify circuit characteristics based on placement criteria. More specifically, there are potential modifications in soft-logic circuit generation during Verilog HDL code synthesis and partial mapping. We propose using a genetic algorithm-based partial mapper during synthesis to adjust soft-logic circuit implementation in order to achieve the desired synthesis goal. We show that the approach provides promising results for a marginal cost in runtime.

Odin II parses the Verilog into an Abstract Syntax Tree AST and optimizes it, in the first and second phases of synthesis. The third phase moves the AST into a high-level netlist representation of the circuit. The fourth phase instantiates high-level netlist components into the available discrete components or explodes them into primitive gates. In the last phase, Odin II optimizes the low-level netlist and generates a BLIF file. Our contribution is in the fourth phase, where Odin II explodes high-level logic into primitives. Here we use a genetic algorithm to aid the decision on which type of a specific soft logic implementation is appropriate for the design goal. The design goal in our experiment is to find a configuration of adders that the footprint of the corresponding netlist would be as close as possible to the desired footprint given by the user. For this purpose, the user should provide the GA with a GivenAreaRatio representing the desired value of the circuit footprint.

By choosing the fixed mutation rate and the ratio of λ over the number of iterations as parameters, we provide users with improvement opportunities based on their system configuration and goals. Although the aforementioned theory is correct, Fig. 5 displays a nuanced enhancement in the value of fitness after a certain point. In other words, the improvement of the fitness value for a more significant combination of parameters than the enhancement of time is subtle. Fig. 6 also shows that for benchmarks with more operations, the fitness improvement is marginal. Based on the graph, we can conclude that the desired results are achieved earlier in substantial benchmarks. Generally, this can only happen because, in larger benchmarks, we explore a broader space. Since, in large search spaces, the variety of configurations are numerous, the GA finds the desired configuration much faster in terms of the area given by the user. The GA achieved an average 16% enhancement in the area while the critical path was decreased by an average of 2.79%. Our approach with constant GA values, i.e., λ equals 8, the number of iterations equals 1024 and mutation rate equivalent to 70%, needs an average 3.49% more time in the entire VTR flow compared with the default version. The extra execution time of the GA highly depends on the benchmark, the number of addition operations and GA variables.

Acknowledgement

I would like to express my thanks to Jean-Philippe Legault and Dr. Kent for their valuable assistance in this project. This article is partial adapted from our paper published at 2020 Rapid System Prototyping (RSP) conference.

Date: August 5, 2020