We are delighted to announce that our recent paper has been accepted as a poster in the 2022 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays (FPGA'22). In this article, we propose a combination of two academic and industrial open-source synthesis tools on the platform of Verilog-to-routing (VTR), a worldwide popular open-source CAD tool. The new VTR front-end improves device utilization and simplifies the flow by automating hard logic decisions with architecture awareness.

Yosys, as a front-end HDL elaborator, is added to the VTR flow to generate coarse-grain netlists. Odin-II is fed by Yosys generated BLIF files to perform the partial mapping. Then, the netlist is optimized by ABC, followed by performing packing and placement by VPR. A binary search over channel width is conducted to find the minimum routable channel width (Wmin). Once routing at the relaxed channel width (1.3 x Wmin) is performed, the critical path delay (CPD) and wire length are measured.

--Abstract:

Verilog-to-routing (VTR) provides users with an entire flow from the Verilog circuit description to a final FPGA programming configuration. The VTR front-end interface for Verilog compilation, Odin-II, lacks support for the Verilog-2005 standard. However, Odin-II provides complex partial mapping for balancing soft logic and hard blocks. Yosys, an open framework for RTL synthesis, provides extensive support for HDLs. However, the Yosys flow forces the user to decide the discrete circuit implementation manually. The approach taken by Yosys is to map all discrete components into available hard blocks or to explode them in low-level logic when not available. This research proposes improving device utilization and simplifying the flow by automating complex logic decisions with architecture awareness. Yosys, as a front-end for generating coarse-grained netlists, and Odin-II, as BLIF elaborator and partial mapper, are integrated into the VTR flow. According to VTR architectures, hard/soft logic trade-off decisions and heterogeneous logic inference have become available for such coarse-grained BLIF files. Yosys+Odin-II demonstrates promising results by lowering resource consumption, shrinking final circuit footprint, and reducing overall routed wire length, while other criteria remain approximately the same. The overall VTR flow runtime is imperceptibly reduced with Yosys+Odin-II, while the capability of the VTR flow to synthesize more complex designs is improved, and the control over an intelligent partial mapper is provided for users.

Links:

• ACM Library - FPGA'22

• VTR Github Repository

Date: November 22nd, 2021