I am honored to announce that our paper, entitled "Desired Footprint by Technology Mapping Modification using a Genetic Algorithm in Odin-II," is published at the 2020 International Workshop on Rapid System Prototyping (RSP). I would like to express my thanks to Jean-Philippe Legault for his precious assistance and Dr. Kent for his supervision.

--Abstract:

Technology mapping is the transformation of a general Boolean logic network into a functional equivalent K-LUT network that can be implemented by the target FPGA device. Because an FPGA architecture is pre-determined, technology mapping is limited to the available resources. However, circuits can be optimized before the low-level synthesis phase. Odin-II, part of the Verilog-to-routing project, is responsible for synthesis and elaboration. In the partial mapping phase of Odin-II, some modifications are still possible for high-level modules-adder, multiplier-when there is no hard block available. When Odin-II performs partial mapping to create soft logic, we can choose which implementation of a high-level module works best with respect to the desired goals: area versus speed. In this paper, we describe a method to modify circuit characteristics based on placement criteria. More specifically, after partial mapping circuit components and during Verilog HDL code synthesis, there are still potential modifications in soft-logic circuit generation. We propose using a genetic algorithm during synthesis to adjust soft-logic circuit implementation in order to achieve the desired synthesis goal. We show that the approach provides promising results for a marginal cost in runtime.

Date: September 24th, 2020